Implementation of fast HEVC encoder based on SIMD and data-level parallelism

Multi-Grain Parallel Accelerate System for H.264 Encoder on ULTRASPARC T2

This paper describes a multi-grain parallel accelerate system for H.264 encoder on UltraSPARC T2 processor. This system integrates pipeline parallelism, frame-level, slice-level, macroblock-level data parallelism and SIMD technology.We use x264, an H.264 video encoder to implement our parallel accelerate system. Our implementation of parallel accelerate system achieves speedup between 10.1x and...

DMATP: A Design Method and Architecture of TU Parallel Processing for 4K HEVC Hardware Encoder

This paper proposes design method and architecture of parallel processing hardware for Transform Units in High Efficiency Video Coding (HEVC). HEVC is the next generation video coding standard which is expected to be used for high resolution broadcasting such as 4K UltraHD. Since HEVC introduces higher complexities and dependencies than previous standard H.264/AVC, hardware designers have to fi...

Time Optimization of HEVC Encoder over X 86 Processors using SIMD Spring 2013 Multimedia Processing

The design and evaluation of hierarchical multi-level parallelisms for H.264 encoder on multi-core architecture

As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates four level parallelisms – framelevel, slice-level, macroblock-level and data-level into one implementation. Ea...

Time Optimization of HEVC Encoder over X86 Processors using SIMD Spring 2013 Multimedia Processing EE5359 Advisor: Dr. K. R. Rao Department of Electrical Engineering University of Texas, Arlington